This invention relates to frequency synthesizer circuitry, and more particularly to frequency synthesizer circuitry that employs a delay line.
Frequency synthesizer circuitry that is based on a delay-locked loop (DLL) typically exhibits better phase noise performance than its phase-locked loop (PLL) counterpart because it has no noise accumulation. A delay line is used in a DLL-based frequency synthesizer, and outputs of delay stages are combined together to produce an output signal of the frequency synthesizer. Such combining of the delay stage outputs may be referred to as edge combining. Edge combining is traditionally achieved using a large number of logical gates, and it typically results in a complex circuit, especially for frequency synthesizers having a large frequency ratio.